This invention relates to a circuit for reproducing a clock signal which is applicable to magnetic tape recorded information playback systems, digital audio disc players, etc., and more particularly, it relates to a circuit to reproduce a clock signal from reproduced signals of digital information recorded on a recording medium after modulation to make self-clocking possible.
Conventional circuits to reproduce clock signals are configured, for example, as shown in FIG. 1(a) and FIG. 2(a), in which band width is compressed according to a modulation system where digital information is predetermined, for example, systems such as M.sup.2 FM, 3PM, etc., and clock signals are reproduced from playback signals of signals containing clock signal information.
The circuit for reproducing a clock signal shown in FIG. 1(a) is comprised of a phase lock loop (PLL) circuit which consists of a 1/4 time delay circuit 1 of the clock signal period T of the input signal, an MFM signal, delay circuits 2, 3, 4, and 5, exclusive OR circuits 6 and 7, inverter 8, AND gates 9 and 10, flip-flop 11, phase comparator 12, and voltage-controlled oscillator (VCO) 13. As shown in FIG. 1(b) (H), pulses having a pulse width of .tau..sub.2 are obtained at the leading edge and trailing edge of the T/4 delayed signal of the MFM signal shown in FIG. 1(b) (A) due to delay circuits 1 and 2, and the exclusive OR circuit 6, and are inputted into the PLL circuit. And, as shown in FIG. 1(b) (F), pulses having a pulse width of .tau..sub.5 corresponding to the output of VCO 13 are obtained due to delay circuits 3, 4, and 5, exclusive OR circuit 7, inverter 8, AND gates 9 and 10, and flip-flop 11, and are inputted into the PLL circuit, their phases compared, and the clock signal is obtained from the output of the VCO 13. In FIG. 1(b), (B), (C), (D), (E), and (G) are output signal waveforms of the exclusive OR circuit 7, VCO 13, AND gate 9, flip-flop 11, and delay circuit 1, respectively.
The clock signal reproduction circuit shown in FIG. 2(a) is comprised of a PLL circuit which consists of a delay circuit 14 comprised of exclusive OR circuits, a delay circuit 15 comprised of inverters, an exclusive OR circuit 16, monostable multivibrator or one shot 17, NAND gates 18 and 19, inverters 20 and 21, flip-flop 22, phase comparator 12, and VCO 13. As shown in FIG. 2(b) (F), pulses with a predetermined time delay are obtained from the leading edge and the trailing edge of the input signal shown in FIG. 2(b) (A) due to the delay circuit 14, exclusive OR circuit 16, and monostable multivibrator 17, and inputted into the phase comparator 12; and as shown in FIG. 2(b) (E), pulses with a predetermined time delay are obtained from the leading edge and trailing edge of the input signal shown in FIG. 2(b) (A) due to the delay circuit 15, NAND gates 18 and 19, inverters 20 and 21, and flip-flop 22, and inputted into the phase comparator 12, their phases compared, and clock signal is obtained from the output of the VCO 13. In FIG. 2(b ), (B), (C), and (D) are signal waveforms of VCO 13, inverter 20, i.e. the set pulse of flip-flop 22, and NAND gate 19, i.e. reset pulse of flip-flop 22.
In the case of conventional clock signal reproduction circuits such as described above, the VCO's oscillation frequency is set to the approximate value of the frequency of the clock signal contained in the input signal or integral multiples thereof, and every time a leading edge or trailing edge of the input signal occurs, the input is applied to the phase comparator and their phases are compared, the PLL circuit is operated, and a clock signal is reproduced. Consequently, in the case of input signals with fluctuating leading edge and trailing edge times, the frequency dividing ratio of the signals between the VCO and phase comparator changes, and the loop gain of the PLL circuit is dependent on the generating time of the above-mentioned leading edge and trailing edge. Thus, there are shortcomings that make it difficult to construct a stable PLL circuit or a PLL circuit having a constant damping factor and a constant frequency zone.
In addition, due to the fact that the interval between the leading edge and trailing edge times of the input signal is not interpolated, when the variable range of VCO is widened, there is a shortcoming that locking occurs at a frequency different from the original clock signal frequency in the input signal, that is, the so-called mislocking phenomenon occurs. Conversely, when the variable range of VCO is restricted in order to prevent the mislocking phenomenon, there is a shortcoming that the response time corresponding to other characteristics of the PLL circuit, for example, capture range, lock range, step phase input, becomes restricted. When using a conventional clock signal reproduction circuit as described above in series as a part of another servo loop, there is a shortcoming which complicates the determination of stable conditions and response characteristics of the servo loop.